Abstract

The goal of the application specific processor synthesis (ASPROS) project is to develop a methodology, hardware, and software support to make the three-month design cycle vision for multimedia processors a reality.

One goal of ASPROS is to circumvent ad-hoc analysis and development schemes and provide the level of automation necessary to effectively search the design space and to quickly generate the optimized variant.  A key focus in ASPROS is parameterization. Parameterization circumvents redundant designs.

A set of projects eventually leading to an optimized multimedia processor synthesis environment has been identified. These projects are

1. Hardware design of a class of micro-sequencers with varying performance and functionality,

2. Development of a general methodology for parameterization of DSP based datapaths, and

3. Development of a micro-sequencer based hardware-software partitioner for the control part of the design.

In the ASPROS project, we will also study power and area estimation and optimization. Motorola's computing systems lab and Northwestern's NuCAD Lab have developed a flat behavioral level power estimation tool in the past five years.

Existing pre-synthesis CAD tools do not provide area estimation capabilities. At best, existing tools perform equation-based analysis to estimate the area. The main problem is that equation-based area estimation ignores the global interconnect and usually provides grossly inaccurate area estimates. The inaccuracy is more severe in deep-submicron regimes. It should be emphasized that interconnect-aware area estimation, or more specifically area planning, is extremely useful for timing and power analysis. Research in the area of incremental floor planning to achieve accurate area estimation will be performed.

Students

• Todd Haverkos

• Vivian Guzmann